EEE 303 (January 2020)


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"There are 10 types of people in this world. Those who understand binary, and those who doesn't."

Welcome to the course on Digital Electronics, where we will explore the very fundamental concepts that makes most of our modern consumer electronic products function.

Office Hours

Tues 12-1pm (Section A) Saturday 12-1pm (Section B) I will be in my office at EEE 222, and students are welcome to drop by with any questions/problems related to the class or for conceptual understanding of the topics. Other than office hours, prior appointment must be made to schedule a meeting. For any course related matter outside the class, preferred medium of communication is email

Course Outline

  • Week 1 - (Brown 5.1, Floyd 2.1-2.10) - Introduction to Course, Introduction to Number Systems and codes. Introduction to verilog
  • Week 2 - (Floyd 3.1-3.7,4 Brown 2.1-2.9) - Analysis and synthesis of digital logic circuits: Basic logic function, Boolean algebra, combinational logic design, minimization of combinational logic (k-map)
  • Week 3 - (Floyd 5, Brown 4) universal logic gates, verilog synthesis with combinational logic
  • Week 4 - (Floyd 6, Brown 7) Decoder, encoder, comparators, binary arithmetic elements and ALU design
  • Week 5 - (Brown 7, Floyd 7) Sequential circuits: different types of latches, flip-flops
  • Week 6 - (Brown 7) Modular sequential logic circuit design: shift registers, counters, and application
  • Week 7 - (Brown 9.1-9.3, 8.1) Asynchronous and synchronous sequential circuits
  • Week 8 - (Brown 7.15, Brown 8) State Machine Design, Algorithmic State Machine (ASM), timing analysis and power optimization of sequential circuits.
  • Week 9 - MOSFET Digital circuits: NMOS inverter, CMOS inverter, CMOS logic circuits, Clocked CMOS logic circuits, transmission gates,
  • Week 10 - (Floyd 11) Memories: classification and architecture, RAM memory cells, Read only memory, data converters
  • Week 11 - (Floyd 15) BJT digital circuits: ECL, TTL, STTL, BiCMOS, Design application A static ECL gate
  • Week 12 - (Brown 6.1) Modular combinational circuit design: pass transistor, pass gates, multiplexer, demultiplexer and their implementation in CMOS

Lecture Notes

Classtest Syllabus

Classtest 1

Contents of Week 1 and Week 2 from above.

Homework Problems

N.B. - Please write the following on the top of the homework:


Student ID:

Course Number: EEE 303

Course Instructor: Dr. Sajid Muhaimin Choudhury

Homework Number: 1A Date of Submission: XX

Homework 1A

An alien species have landed on earth that have four hands with 9 fingers on each hand (36 fingers in total). They follow a base-36 number system. We will define variable 'X' and variable 'Y' in their number system. The first 3 letters of your first name is variable X, last 3 letters of your last name is variable Y, first letter of your last name is variable Z (For example for Mahbubur Rahman, X=MAH, Y=MAN, Z=R, X,Y,Z are in base-36)

Problem 1: Convert X and Y to decimal, binary, hexadecimal and octal number

Problem 2: In binary and decimal, compute X+Y, X-Y. Compute 2's complement of Y in binary and recompute X-Y

Problem 3: Represent the floating point number X.Y in IEEE single precision floating point number

Problem 4: Convert X to grey code and ASCII

Problem 5: Install Altera Quartus. Show the value of Z in Binary and hexadecimal. Attach a printed copy of the waveform with your file

Homework 1B

Problem 1: Convert Z from problem 1 into binary and take the first 8 bits from the MSB. Assume the function f(A,B,C) is defined as these first 8 bits denoted by 'G'. Write the truth table of the function, write the function in terms of Sum of Products and Product of Sum form, and draw a K-map of the function and reduce it to minimum form.

Problem 2: Write a verilog code that generates fibonacci sequence of a number. (

Fibonacci number, Fn = F(n-1) + F_(n-2); F_0 = 1; F_1 = 1

Input: clock Output: 16 bit fibonacci number

each time clock changes state from 0 to 1, the fibonacci number output is changed, showing from F_0, F_1, F_2 etc.

Case 1: F_0 = 1; F_1 = 1; (Regular fibonacci number) Case 2: F_0 = G; and F_1 = 1;

Show (print) output for both cases for 16 different clock changes


  • Stephen Brown and Zvonko Vranesic, "Fundamentals of Digital Logic with Verilog Design"
  • Thomas L. Floyd, "Digital Fundamentals Eleventh Edition"
  • Morris Mano and Michael Ciletti, "Digital Design with an Introduction to VerilogHDL"

Additional Resources